The present invention relates to programmable logic devices (PLDs). In particular, the present invention relates to a nonvolatile configuration memory as part of a PLD.
FIG. 1 generally shows a PLD 100. A PLD is generally an integrated circuit device with some degree of programmability or configurability. As such, PLDs are good choices for device controllers, because they can be easily configured to operate in a wide variety of potential device environments.
The PLD 100 is exemplary of many PLDs. The PLD 100 includes an interconnect 102 and various function blocks. (The function blocks may also be referred to in the industry as IP blocks.) Exemplary function blocks include a logic block 104, a memory block 106, a digital signal processor (DSP) block 108, input/output (I/O) blocks 110, a general-purpose processor block 112, a phase-locked loop block 114, and a configuration block 116. The interconnect connects the function blocks together. Based on the intended use of the PLD, the interconnect 102 and the various function blocks may be configured in various ways.
When the PLD 100 is powered up, configuration information is transferred from a nonvolatile memory to a static random access memory (SRAM). To reduce the configuration time, it is desirable that the nonvolatile memory be able to output the configuration information at a high rate. However, when the nonvolatile memory is outputting information at a high rate, it consumes a relatively large amount of power.
Furthermore, on a PLD, space is at a premium. When space issues arise, designers must make hard decisions regarding which function blocks to eliminate or reduce in size. A memory block is one type of function block that is often chosen to be eliminated or reduced in size to overcome space issues.
There is a need for a PLD with a fast configuration time, that has a relatively larger amount of memory than certain existing PLDs, and that does not consume too much power.